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Eighth ACM/IEEE International Conference on
Formal Methods and Models for Codesign

Grenoble, France
July 26-28, 2010

Memocode 2010 was great!
Thanks a lot to all the sponsors, reviewers, panelists, speakers, and attendees.

Pictures from Memocode 2010

List of Accepted Papers

Sidharta Andalam, Partha Roop and Alain Girault. Predictable multithreading of embedded applications using PRET-C

Emil Axelsson, Koen Claessen, Gergely Devai, Zoltan Horvath, Karin Keijzer, Bo Lyckgard, Anders Persson, Mary Sheeran, Josef Svenningsson and Andras Vajda. Feldspar: A Domain Specific Language for Digital Signal Processing algorithms

Bryan Brady, Randal E. Bryant, Sanjit A. Seshia and John O'Leary. ATLAS: Automatic Term-Level Abstraction of RTL Designs

Roberto Bruttomesso, Edgar Pek and Natasha Sharygina. A Flexible Schema for Generating Explanations in Lazy Theory Propagation

Tevfik Bultan, Fang Yu and Aysu Betin Can. Modular Verification of Synchronization with Reentrant Locks

Nirav Dave, Man Cheuk Ng, Michael Pellauer and Arvind. A Design Flow Based on Modular Refinement

Luca Ferro and Laurence Pierre. Enhancing the Assertion-Based Verification of TLM Designs with Reentrancy

Mike Gemuende, Jens Brandt and Klaus Schneider. Compilation of Imperative Synchronous Programs with Refined Clocks

David Greaves and Satnam Singh. Designing Application Specific Circuits with Concurrent C# Programs

Daniel Grosse, Hoang M. Le and Rolf Drechsler. Proving Transaction and System-level Properties of Untimed SystemC TLM Designs

Franjo Ivancic, Malay K. Ganai, Sriram Sankaranarayanan and Aarti Gupta. Numerical stability analysis of floating-point computations using software model checking

Patrick Meredith, Michael Katelman, Jose Mesegeur and Grigore Rosu. A Formal Executable Semantics of Verilog

Julio Peralta, Thierry Gautier and Loic Besnard. LTSs for Translation Validation of (multi-clocked) Signal specifications

Deian Tabakov and Moshe Vardi. Monitoring Temporal SystemC Properties

Bin Xue, Sandeep Shukla and Sekharipuram Ravi. Minimizing Back Pressure for Latency Insensitive System Synthesis